On 17/07/17 18:06, Mathieu Poirier wrote:
On Fri, Jul 14, 2017 at 02:04:19PM +0100, Suzuki K Poulose wrote:
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheab
On Fri, Jul 14, 2017 at 02:04:19PM +0100, Suzuki K Poulose wrote:
> This patch cleans up how we setup the AXICTL register on
> TMC ETR. At the moment we don't set the CacheCtrl bits, which
> drives the arcache and awcache bits on AXI bus specifying the
> cacheablitiy. Set this to Write-back Read an
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
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