Re: [PATCH v3 15/20] perf arm-spe: Remove size condition checking for events

2020-10-23 Thread André Przywara
On 22/10/2020 15:58, Leo Yan wrote: > In the Armv8 ARM (ARM DDI 0487F.c), chapter "D10.2.6 Events packet", it > describes the event bit is valid with specific payload requirement. For > example, the Last Level cache access event, the bit is defined as: > > E[8], byte 1 bit [0], when SZ == 0b01

[PATCH v3 15/20] perf arm-spe: Remove size condition checking for events

2020-10-22 Thread Leo Yan
In the Armv8 ARM (ARM DDI 0487F.c), chapter "D10.2.6 Events packet", it describes the event bit is valid with specific payload requirement. For example, the Last Level cache access event, the bit is defined as: E[8], byte 1 bit [0], when SZ == 0b01 , when SZ == 0b10 , or wh