[PATCH v3 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT

cache_line_size is derived from CTR_EL0.CWG field and is called mostly for I/O device drivers. For HiSilicon certain plantform, like the Kunpeng920 server SoC, cache line sizes are different between L1/2 cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, but CTR_EL0.CWG is m

Re: [PATCH v3 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT

On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote: > cache_line_size is derived from CTR_EL0.CWG field and is called mostly > for I/O device drivers. For HiSilicon certain plantform, like the > Kunpeng920 server SoC, cache line sizes are different between L1/2 > cache and L3 cache while

Re: [PATCH v3 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT

Hi Greg, On 2019/5/27 14:08, Greg KH wrote: > On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote: >> cache_line_size is derived from CTR_EL0.CWG field and is called mostly >> for I/O device drivers. For HiSilicon certain plantform, like the >> Kunpeng920 server SoC, cache line sizes are