RE: [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

2017-12-14 Thread Dhaval Rajeshbhai Shah
rg; > mark.rutl...@arm.com > Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > michal.si...@xilinx.com; Hyun Kwon ; Dhaval Rajeshbhai > Shah > Subject: Re: [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver > > On 12/13/2017 09:55 PM, Dhaval Shah

Re: [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

2017-12-14 Thread Randy Dunlap
On 12/13/2017 09:55 PM, Dhaval Shah wrote: > Xilinx ZYNQMP logicoreIP Init driver is based on the new > LogiCoreIP design created. This driver provides the processing system > and programmable logic isolation. Set the frequency based on the clock > information get from the logicoreIP register set.

[PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

2017-12-13 Thread Dhaval Shah
Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. It is put in drivers/misc as there is no subsystem