Hi Vinod,
On 2020/07/16 15:37, Vinod Koul wrote:
On 16-07-20, 11:43, Kunihiko Hayashi wrote:
+static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv)
+{
+ int i;
+ u32 val;
+
+ /* setup port parameter */
+ val = readl(priv->base + TXCTRL0);
+ val
On 16-07-20, 11:43, Kunihiko Hayashi wrote:
> +static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv)
> +{
> + int i;
> + u32 val;
> +
> + /* setup port parameter */
> + val = readl(priv->base + TXCTRL0);
> + val &= ~TXCTRL0_AMP_G3_MASK;
> + val |= FIELD_
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier-a
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