On Thu, Jul 28, 2016 at 05:17:06PM -0600, Jason Gunthorpe wrote:
> On Thu, Jul 28, 2016 at 04:01:41PM -0700, Dmitry Torokhov wrote:
>
> > > + u8 tx_buf[MAX_SPI_FRAMESIZE];
> > > + u8 rx_buf[MAX_SPI_FRAMESIZE];
> >
> > Both of these need to be annotated as "cacheline_aligned" since we
> > eye
On Thu, Jul 28, 2016 at 05:17:06PM -0600, Jason Gunthorpe wrote:
> On Thu, Jul 28, 2016 at 04:01:41PM -0700, Dmitry Torokhov wrote:
>
> > > + u8 tx_buf[MAX_SPI_FRAMESIZE];
> > > + u8 rx_buf[MAX_SPI_FRAMESIZE];
> >
> > Both of these need to be annotated as "cacheline_aligned" since we
> > eye
On Thu, Jul 28, 2016 at 04:01:41PM -0700, Dmitry Torokhov wrote:
> > + u8 tx_buf[MAX_SPI_FRAMESIZE];
> > + u8 rx_buf[MAX_SPI_FRAMESIZE];
>
> Both of these need to be annotated as "cacheline_aligned" since we
> eye them for use in DMA transfers.
Huh. That sure looks true to me..
We make
On Thu, Jul 28, 2016 at 04:01:41PM -0700, Dmitry Torokhov wrote:
> > + u8 tx_buf[MAX_SPI_FRAMESIZE];
> > + u8 rx_buf[MAX_SPI_FRAMESIZE];
>
> Both of these need to be annotated as "cacheline_aligned" since we
> eye them for use in DMA transfers.
Huh. That sure looks true to me..
We make
On Wed, Jul 27, 2016 at 09:25:17PM -0700, Andrey Pronin wrote:
> Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
> firmware. The firmware running on the currently supported H1
> Secure Microcontroller requires a special driver to handle its
> specifics:
> - need to ensure a
On Wed, Jul 27, 2016 at 09:25:17PM -0700, Andrey Pronin wrote:
> Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
> firmware. The firmware running on the currently supported H1
> Secure Microcontroller requires a special driver to handle its
> specifics:
> - need to ensure a
Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
firmware. The firmware running on the currently supported H1
Secure Microcontroller requires a special driver to handle its
specifics:
- need to ensure a certain delay between spi transactions, or else
the chip may miss some part
Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
firmware. The firmware running on the currently supported H1
Secure Microcontroller requires a special driver to handle its
specifics:
- need to ensure a certain delay between spi transactions, or else
the chip may miss some part
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