Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-10-02 Thread Vignesh R
On 9/24/2017 6:43 PM, Marek Vasut wrote: > On 09/24/2017 02:33 PM, Vignesh R wrote: >> >> >> On 9/24/2017 5:29 PM, Marek Vasut wrote: >>> On 09/24/2017 12:59 PM, Vignesh R wrote: As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay e

Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-24 Thread Marek Vasut
On 09/24/2017 02:33 PM, Vignesh R wrote: > > > On 9/24/2017 5:29 PM, Marek Vasut wrote: >> On 09/24/2017 12:59 PM, Vignesh R wrote: >>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access >>> Controller programming sequence, a delay equal to couple of QSPI master >>> clock(~5ns) is

Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-24 Thread Vignesh R
On 9/24/2017 5:29 PM, Marek Vasut wrote: > On 09/24/2017 12:59 PM, Vignesh R wrote: >> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access >> Controller programming sequence, a delay equal to couple of QSPI master >> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START b

Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-24 Thread Marek Vasut
On 09/24/2017 12:59 PM, Vignesh R wrote: > As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access > Controller programming sequence, a delay equal to couple of QSPI master > clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and > writing data to the flash. Introduce a

[PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-24 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this an