Quoting Yixun Lan (2018-03-27 19:50:48)
> + [CLKID_AO_SAR_ADC_CLK] = &axg_saradc_gate,
> +};
> +
> +static struct clk_hw_onecell_data axg_aoclk_onecell_data = {
const?
> + .hws = {
> + [CLKID_AO_REMOTE] = &remote_ao.hw,
> + [CLKID_AO_I2C_MASTER] =
From: Qiufang Dai
Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.
Signed-off-by: Qiufang Dai
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Makefile| 2 +-
drivers/clk/meson/axg-aoclk.c | 164 ++
drive
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