Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2017-01-03 Thread Lee Jones
On Tue, 06 Dec 2016, Andrew Jeffery wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon device for ar

Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2016-12-12 Thread Andrew Jeffery
On Mon, 2016-12-12 at 09:30 -0600, Rob Herring wrote: > On Tue, Dec 06, 2016 at 01:53:19PM +1100, Andrew Jeffery wrote: > > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > > on bits in both the System Control Unit and the LPC Host Controller. > > > > The Aspeed LPC Host

Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2016-12-12 Thread Rob Herring
On Tue, Dec 06, 2016 at 01:53:19PM +1100, Andrew Jeffery wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range

Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2016-12-08 Thread Andrew Jeffery
On Thu, 2016-12-08 at 12:42 +1030, Joel Stanley wrote: > > On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery wrote: > > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > > on bits in both the System Control Unit and the LPC Host Controller. > > > > The Aspeed LPC Host Contro

Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2016-12-07 Thread Joel Stanley
On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon dev

Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2016-12-07 Thread Linus Walleij
On Tue, Dec 6, 2016 at 3:53 AM, Andrew Jeffery wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon de

[PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

2016-12-05 Thread Andrew Jeffery
The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux