On Monday, 11 June 2018 14:50:13 MSK Boris Brezillon wrote:
> On Mon, 11 Jun 2018 14:45:45 +0300
>
> Dmitry Osipenko wrote:
> > On Sunday, 10 June 2018 18:32:02 MSK Boris Brezillon wrote:
> > > On Sun, 10 Jun 2018 18:00:06 +0300
> > >
> > > Dmitry Osipenko wrote:
> > > > > >> That seems a lot
On Monday, 11 June 2018 14:50:13 MSK Boris Brezillon wrote:
> On Mon, 11 Jun 2018 14:45:45 +0300
>
> Dmitry Osipenko wrote:
> > On Sunday, 10 June 2018 18:32:02 MSK Boris Brezillon wrote:
> > > On Sun, 10 Jun 2018 18:00:06 +0300
> > >
> > > Dmitry Osipenko wrote:
> > > > > >> That seems a lot
On Mon, 11 Jun 2018 14:45:45 +0300
Dmitry Osipenko wrote:
> On Sunday, 10 June 2018 18:32:02 MSK Boris Brezillon wrote:
> > On Sun, 10 Jun 2018 18:00:06 +0300
> >
> > Dmitry Osipenko wrote:
> > > > >> That seems a lot of work for a code path I do not intend to ever use
> > > > >> :-)
> > >
On Mon, 11 Jun 2018 14:45:45 +0300
Dmitry Osipenko wrote:
> On Sunday, 10 June 2018 18:32:02 MSK Boris Brezillon wrote:
> > On Sun, 10 Jun 2018 18:00:06 +0300
> >
> > Dmitry Osipenko wrote:
> > > > >> That seems a lot of work for a code path I do not intend to ever use
> > > > >> :-)
> > >
On Sunday, 10 June 2018 18:32:02 MSK Boris Brezillon wrote:
> On Sun, 10 Jun 2018 18:00:06 +0300
>
> Dmitry Osipenko wrote:
> > > >> That seems a lot of work for a code path I do not intend to ever use
> > > >> :-)
> > > >
> > > > Are you sure that resetting HW resets the timing and other
On Sunday, 10 June 2018 18:32:02 MSK Boris Brezillon wrote:
> On Sun, 10 Jun 2018 18:00:06 +0300
>
> Dmitry Osipenko wrote:
> > > >> That seems a lot of work for a code path I do not intend to ever use
> > > >> :-)
> > > >
> > > > Are you sure that resetting HW resets the timing and other
On Sun, 10 Jun 2018 18:00:06 +0300
Dmitry Osipenko wrote:
> > >> That seems a lot of work for a code path I do not intend to ever use :-)
> > >>
> > >
> > > Are you sure that resetting HW resets the timing and other registers
> > > configuration? Reset implementation is HW-specific, like for
On Sun, 10 Jun 2018 18:00:06 +0300
Dmitry Osipenko wrote:
> > >> That seems a lot of work for a code path I do not intend to ever use :-)
> > >>
> > >
> > > Are you sure that resetting HW resets the timing and other registers
> > > configuration? Reset implementation is HW-specific, like for
On Sunday, 10 June 2018 14:09:24 MSK Stefan Agner wrote:
> On 09.06.2018 14:21, Dmitry Osipenko wrote:
> > On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
> >> On 01.06.2018 11:20, Dmitry Osipenko wrote:
> >> > On 01.06.2018 01:16, Stefan Agner wrote:
> >> >> Add support for the NAND
On Sunday, 10 June 2018 14:09:24 MSK Stefan Agner wrote:
> On 09.06.2018 14:21, Dmitry Osipenko wrote:
> > On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
> >> On 01.06.2018 11:20, Dmitry Osipenko wrote:
> >> > On 01.06.2018 01:16, Stefan Agner wrote:
> >> >> Add support for the NAND
On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller found on NVIDIA
>> >> Tegra 2 SoCs. This
On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller found on NVIDIA
>> >> Tegra 2 SoCs. This
On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
> On 01.06.2018 11:20, Dmitry Osipenko wrote:
> > On 01.06.2018 01:16, Stefan Agner wrote:
> >> Add support for the NAND flash controller found on NVIDIA
> >> Tegra 2 SoCs. This implementation does not make use of the
> >> command queue
On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
> On 01.06.2018 11:20, Dmitry Osipenko wrote:
> > On 01.06.2018 01:16, Stefan Agner wrote:
> >> Add support for the NAND flash controller found on NVIDIA
> >> Tegra 2 SoCs. This implementation does not make use of the
> >> command queue
On Fri, 1 Jun 2018 00:16:35 +0200
Stefan Agner wrote:
> +
> +static int tegra_nand_chips_init(struct device *dev,
> + struct tegra_nand_controller *ctrl)
> +{
> + struct device_node *np = dev->of_node;
> + struct device_node *np_nand;
> + int nchips =
On Fri, 1 Jun 2018 00:16:35 +0200
Stefan Agner wrote:
> +
> +static int tegra_nand_chips_init(struct device *dev,
> + struct tegra_nand_controller *ctrl)
> +{
> + struct device_node *np = dev->of_node;
> + struct device_node *np_nand;
> + int nchips =
On Sat, 9 Jun 2018 08:46:15 +0200
Boris Brezillon wrote:
> On Sat, 9 Jun 2018 08:41:57 +0200
> Boris Brezillon wrote:
>
> > On Sat, 09 Jun 2018 08:23:51 +0200
> > Stefan Agner wrote:
> >
> > > On 09.06.2018 07:52, Boris Brezillon wrote:
> > > > On Fri, 08 Jun 2018 23:51:01 +0200
> > > >
On Sat, 9 Jun 2018 08:46:15 +0200
Boris Brezillon wrote:
> On Sat, 9 Jun 2018 08:41:57 +0200
> Boris Brezillon wrote:
>
> > On Sat, 09 Jun 2018 08:23:51 +0200
> > Stefan Agner wrote:
> >
> > > On 09.06.2018 07:52, Boris Brezillon wrote:
> > > > On Fri, 08 Jun 2018 23:51:01 +0200
> > > >
On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner wrote:
>> >
>> >
>> >> >
>> >> > void tegra_nand_controller_reset(struct
On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner wrote:
>> >
>> >
>> >> >
>> >> > void tegra_nand_controller_reset(struct
On Sat, 9 Jun 2018 08:41:57 +0200
Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
> > On 09.06.2018 07:52, Boris Brezillon wrote:
> > > On Fri, 08 Jun 2018 23:51:01 +0200
> > > Stefan Agner wrote:
> > >
> > >
> > >> >
> > >> > void
On Sat, 9 Jun 2018 08:41:57 +0200
Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
> > On 09.06.2018 07:52, Boris Brezillon wrote:
> > > On Fri, 08 Jun 2018 23:51:01 +0200
> > > Stefan Agner wrote:
> > >
> > >
> > >> >
> > >> > void
On Sat, 09 Jun 2018 08:23:51 +0200
Stefan Agner wrote:
> On 09.06.2018 07:52, Boris Brezillon wrote:
> > On Fri, 08 Jun 2018 23:51:01 +0200
> > Stefan Agner wrote:
> >
> >
> >> >
> >> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
> >> > {
> >> > int err;
> >> >
>
On Sat, 09 Jun 2018 08:23:51 +0200
Stefan Agner wrote:
> On 09.06.2018 07:52, Boris Brezillon wrote:
> > On Fri, 08 Jun 2018 23:51:01 +0200
> > Stefan Agner wrote:
> >
> >
> >> >
> >> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
> >> > {
> >> > int err;
> >> >
>
On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner wrote:
>
>
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disable_irq(ctrl->irq);
>> >
>> >err =
On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner wrote:
>
>
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disable_irq(ctrl->irq);
>> >
>> >err =
On Fri, 1 Jun 2018 00:16:35 +0200
Stefan Agner wrote:
> +
> +static const struct of_device_id tegra_nand_of_match[] = {
> + { .compatible = "nvidia,tegra20-nand" },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver tegra_nand_driver = {
> + .driver = {
> +
On Fri, 1 Jun 2018 00:16:35 +0200
Stefan Agner wrote:
> +
> +static const struct of_device_id tegra_nand_of_match[] = {
> + { .compatible = "nvidia,tegra20-nand" },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver tegra_nand_driver = {
> + .driver = {
> +
On Fri, 08 Jun 2018 23:51:01 +0200
Stefan Agner wrote:
> >
> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
> > {
> > int err;
> >
> > disable_irq(ctrl->irq);
> >
> > err = reset_control_reset(ctrl->rst);
> > if (err) {
> >
On Fri, 08 Jun 2018 23:51:01 +0200
Stefan Agner wrote:
> >
> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
> > {
> > int err;
> >
> > disable_irq(ctrl->irq);
> >
> > err = reset_control_reset(ctrl->rst);
> > if (err) {
> >
On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode.
On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode.
Hi Randolph,
On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data
Hi Randolph,
On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data
Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware
Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware
On 01.06.2018 01:16, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the
On 01.06.2018 01:16, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the
Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.
Signed-off-by: Lucas Stach
Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.
Signed-off-by: Lucas Stach
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