Re: [PATCH v3 4/7] clk: st: clkgen-pll: embed soc clock outputs within compatible data

Hi Alain 3/30/21 10:51 PM, Alain Volmat wrote: > In order to avoid relying on the old style description via the DT > clock-output-names, add compatible data describing the flexgen > outputs clocks for all STiH407/STiH410 and STiH418 SOCs. > > In order to ease transition between the two methods, t

[PATCH v3 4/7] clk: st: clkgen-pll: embed soc clock outputs within compatible data

In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing t