On 2021/3/5 0:12, Sean Christopherson wrote:
On Thu, Mar 04, 2021, Xu, Like wrote:
Hi Sean,
Thanks for your detailed review on the patch set.
On 2021/3/4 0:58, Sean Christopherson wrote:
On Wed, Mar 03, 2021, Like Xu wrote:
@@ -348,10 +352,26 @@ static bool
On Thu, Mar 04, 2021, Xu, Like wrote:
> Hi Sean,
>
> Thanks for your detailed review on the patch set.
>
> On 2021/3/4 0:58, Sean Christopherson wrote:
> > On Wed, Mar 03, 2021, Like Xu wrote:
> > > @@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct
> > > kvm_vcpu *vcpu,
Hi Sean,
Thanks for your detailed review on the patch set.
On 2021/3/4 0:58, Sean Christopherson wrote:
On Wed, Mar 03, 2021, Like Xu wrote:
@@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct
kvm_vcpu *vcpu,
return true;
}
+/*
+ * Check if the requested
On Wed, Mar 03, 2021, Like Xu wrote:
> @@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct
> kvm_vcpu *vcpu,
> return true;
> }
>
> +/*
> + * Check if the requested depth values is supported
> + * based on the bits [0:7] of the guest cpuid.1c.eax.
> + */
> +static
The number of Arch LBR entries available for recording operations
is dictated by the value in MSR_ARCH_LBR_DEPTH.DEPTH. The supported
LBR depth values can be found in CPUID.(EAX=01CH, ECX=0):EAX[7:0]
and for each bit "n" set in this field, the MSR_ARCH_LBR_DEPTH.DEPTH
value of "8*(n+1)" is
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