Hi James,
On 2017/5/9 1:27, James Morse wrote:
> Hi Xiongfeng Wang,
>
> On 28/04/17 03:55, Xiongfeng Wang wrote:
>> It is ok to just ignore the process following the ESB instruction in
>> el0_sync, because the process will be sent SIGBUS signal.
I don't understand. How will
Hi James,
On 2017/5/9 1:27, James Morse wrote:
> Hi Xiongfeng Wang,
>
> On 28/04/17 03:55, Xiongfeng Wang wrote:
>> It is ok to just ignore the process following the ESB instruction in
>> el0_sync, because the process will be sent SIGBUS signal.
I don't understand. How will
Hi Xiongfeng Wang,
On 28/04/17 03:55, Xiongfeng Wang wrote:
>>> >> It is ok to just ignore the process following the ESB instruction in
>>> >> el0_sync, because the process will be sent SIGBUS signal.
>> >
>> > I don't understand. How will Linux know the process caused an error if we
>> >
Hi Xiongfeng Wang,
On 28/04/17 03:55, Xiongfeng Wang wrote:
>>> >> It is ok to just ignore the process following the ESB instruction in
>>> >> el0_sync, because the process will be sent SIGBUS signal.
>> >
>> > I don't understand. How will Linux know the process caused an error if we
>> >
Hi James,
Thanks for your explanation and suggests.
On 2017/4/25 1:14, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 21/04/17 12:33, Xiongfeng Wang wrote:
>> On 2017/4/20 16:52, James Morse wrote:
>>> On 19/04/17 03:37, Xiongfeng Wang wrote:
On 2017/4/18 18:51, James Morse wrote:
>
Hi James,
Thanks for your explanation and suggests.
On 2017/4/25 1:14, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 21/04/17 12:33, Xiongfeng Wang wrote:
>> On 2017/4/20 16:52, James Morse wrote:
>>> On 19/04/17 03:37, Xiongfeng Wang wrote:
On 2017/4/18 18:51, James Morse wrote:
>
Hi Wang Xiongfeng,
On 21/04/17 12:33, Xiongfeng Wang wrote:
> On 2017/4/20 16:52, James Morse wrote:
>> On 19/04/17 03:37, Xiongfeng Wang wrote:
>>> On 2017/4/18 18:51, James Morse wrote:
The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
describe a way to
Hi Wang Xiongfeng,
On 21/04/17 12:33, Xiongfeng Wang wrote:
> On 2017/4/20 16:52, James Morse wrote:
>> On 19/04/17 03:37, Xiongfeng Wang wrote:
>>> On 2017/4/18 18:51, James Morse wrote:
The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
describe a way to
Hi James,
Thanks for your reply.
On 2017/4/20 16:52, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 19/04/17 03:37, Xiongfeng Wang wrote:
>> On 2017/4/18 18:51, James Morse wrote:
>>> The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
>>> describe a way to inject these
Hi James,
Thanks for your reply.
On 2017/4/20 16:52, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 19/04/17 03:37, Xiongfeng Wang wrote:
>> On 2017/4/18 18:51, James Morse wrote:
>>> The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
>>> describe a way to inject these
Hi XiuQi,
On 2017/3/30 18:31, Xie XiuQi wrote:
> Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
> is used to synchronize Unrecoverable errors. That is, containable errors
> architecturally consumed by the PE and not silently propagated.
>
> With ESB it is generally possible
Hi XiuQi,
On 2017/3/30 18:31, Xie XiuQi wrote:
> Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
> is used to synchronize Unrecoverable errors. That is, containable errors
> architecturally consumed by the PE and not silently propagated.
>
> With ESB it is generally possible
Hi Wang Xiongfeng,
On 19/04/17 03:37, Xiongfeng Wang wrote:
> On 2017/4/18 18:51, James Morse wrote:
>> The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
>> describe a way to inject these as they are generated by the CPU.
>>
>> Am I right in thinking you want this to use
Hi Wang Xiongfeng,
On 19/04/17 03:37, Xiongfeng Wang wrote:
> On 2017/4/18 18:51, James Morse wrote:
>> The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
>> describe a way to inject these as they are generated by the CPU.
>>
>> Am I right in thinking you want this to use
Hi James,
Thanks for your reply.
On 2017/4/18 18:51, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 18/04/17 02:09, Xiongfeng Wang wrote:
>> I have some confusion about the RAS feature when VHE is enabled. Does RAS
>> spec support
>> the situation when VHE is enabled. When VHE is disabled, the
Hi James,
Thanks for your reply.
On 2017/4/18 18:51, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 18/04/17 02:09, Xiongfeng Wang wrote:
>> I have some confusion about the RAS feature when VHE is enabled. Does RAS
>> spec support
>> the situation when VHE is enabled. When VHE is disabled, the
Hi Wang Xiongfeng,
On 18/04/17 02:09, Xiongfeng Wang wrote:
> I have some confusion about the RAS feature when VHE is enabled. Does RAS
> spec support
> the situation when VHE is enabled. When VHE is disabled, the hyperviosr
> delegates the error
> exception to EL1 by setting HCR_EL2.VSE to 1,
Hi Wang Xiongfeng,
On 18/04/17 02:09, Xiongfeng Wang wrote:
> I have some confusion about the RAS feature when VHE is enabled. Does RAS
> spec support
> the situation when VHE is enabled. When VHE is disabled, the hyperviosr
> delegates the error
> exception to EL1 by setting HCR_EL2.VSE to 1,
Hi Mark,
I have some confusion about the RAS feature when VHE is enabled. Does RAS spec
support
the situation when VHE is enabled. When VHE is disabled, the hyperviosr
delegates the error
exception to EL1 by setting HCR_EL2.VSE to 1, and this will inject a virtual
SEI into OS.
My understanding
Hi Mark,
I have some confusion about the RAS feature when VHE is enabled. Does RAS spec
support
the situation when VHE is enabled. When VHE is disabled, the hyperviosr
delegates the error
exception to EL1 by setting HCR_EL2.VSE to 1, and this will inject a virtual
SEI into OS.
My understanding
Hi Mark,
Thanks for your comments.
On 2017/4/13 18:51, Mark Rutland wrote:
> Hi,
>
> On Thu, Mar 30, 2017 at 06:31:07PM +0800, Xie XiuQi wrote:
>> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
>> index f20c64a..22f9c90 100644
>> --- a/arch/arm64/include/asm/esr.h
>>
Hi Mark,
Thanks for your comments.
On 2017/4/13 18:51, Mark Rutland wrote:
> Hi,
>
> On Thu, Mar 30, 2017 at 06:31:07PM +0800, Xie XiuQi wrote:
>> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
>> index f20c64a..22f9c90 100644
>> --- a/arch/arm64/include/asm/esr.h
>>
Hi,
On Thu, Mar 30, 2017 at 06:31:07PM +0800, Xie XiuQi wrote:
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index f20c64a..22f9c90 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -106,6 +106,20 @@
> #define ESR_ELx_AR
Hi,
On Thu, Mar 30, 2017 at 06:31:07PM +0800, Xie XiuQi wrote:
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index f20c64a..22f9c90 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -106,6 +106,20 @@
> #define ESR_ELx_AR
Hi Xiuqi,
On 2017/3/30 18:31, Xie XiuQi wrote:
> Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
> is used to synchronize Unrecoverable errors. That is, containable errors
> architecturally consumed by the PE and not silently propagated.
>
> With ESB it is generally possible
Hi Xiuqi,
On 2017/3/30 18:31, Xie XiuQi wrote:
> Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
> is used to synchronize Unrecoverable errors. That is, containable errors
> architecturally consumed by the PE and not silently propagated.
>
> With ESB it is generally possible
Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
is used to synchronize Unrecoverable errors. That is, containable errors
architecturally consumed by the PE and not silently propagated.
With ESB it is generally possible to isolate an unrecoverable error
between two ESB
Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
is used to synchronize Unrecoverable errors. That is, containable errors
architecturally consumed by the PE and not silently propagated.
With ESB it is generally possible to isolate an unrecoverable error
between two ESB
Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
is used to synchronize Unrecoverable errors. That is, containable errors
architecturally consumed by the PE and not silently propagated.
With ESB it is generally possible to isolate an unrecoverable error
between two ESB
Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
is used to synchronize Unrecoverable errors. That is, containable errors
architecturally consumed by the PE and not silently propagated.
With ESB it is generally possible to isolate an unrecoverable error
between two ESB
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