Re: [PATCH v3 7/9] clk: mediatek: Fix asymmetrical PLL enable and disable control

On 03/09/2020 05:22, Weiyi Lu wrote: The en_mask actually is a combination of divider enable mask and pll enable bit(bit0). Before this patch, we enabled both divider mask and bit0 in prepare(), but only cleared the bit0 in unprepare(). Now, setting the enable register(CON0) in 2 steps: first

[PATCH v3 7/9] clk: mediatek: Fix asymmetrical PLL enable and disable control

The en_mask actually is a combination of divider enable mask and pll enable bit(bit0). Before this patch, we enabled both divider mask and bit0 in prepare(), but only cleared the bit0 in unprepare(). Now, setting the enable register(CON0) in 2 steps: first divider mask, then bit0 during prepare(),