On 2021/3/5 0:31, Sean Christopherson wrote:
Paolo, any thoughts on how to keep supported_xss aligned with support_xcr0,
without spreading the logic around too much?
From 58be4152ced441395dfc439f446c5ad53bd48576 Mon Sep 17 00:00:00 2001
From: Like Xu
Date: Thu, 4 Mar 2021 13:21:38 +0800
On Thu, Mar 04, 2021, Like Xu wrote:
> On 2021/3/4 2:03, Sean Christopherson wrote:
> > if (vmx_umip_emulated())
> > kvm_cpu_cap_set(X86_FEATURE_UMIP);
> >
> > /* CPUID 0xD.1 */
> > - supported_xss = 0;
> > if (!cpu_has_vmx_xsaves())
> >
On 2021/3/4 2:03, Sean Christopherson wrote:
On Wed, Mar 03, 2021, Like Xu wrote:
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 034708a3df20..ec4593e0ee6d 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7268,6 +7268,8 @@ static __init void
On Wed, Mar 03, 2021, Like Xu wrote:
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 034708a3df20..ec4593e0ee6d 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -7268,6 +7268,8 @@ static __init void vmx_set_cpu_caps(void)
> supported_xss = 0;
>
On processors whose XSAVE feature set supports XSAVES and XRSTORS,
the availability of support for Architectural LBR configuration state save
and restore can be determined from CPUID.(EAX=0DH, ECX=1):EDX:ECX[bit 15].
The detailed leaf for Arch LBRs is enumerated in CPUID.(EAX=0DH, ECX=0FH).
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