On Tue, 2019-01-15 at 11:22 +0100, Thomas Gleixner wrote:
> On Thu, 20 Dec 2018, Lubomir Rintel wrote:
>
> > On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
> > and 72 interrupts. Don't reset the "route to SP" bit (4).
> >
> > I'm just assuming the bit 4 is the "route to
On Thu, 20 Dec 2018, Lubomir Rintel wrote:
> On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
> and 72 interrupts. Don't reset the "route to SP" bit (4).
>
> I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
> SP-based keyboard for me and defines
> ICU_
On Thu, 2018-12-20 at 22:55 +0100, Lubomir Rintel wrote:
> On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
> and 72 interrupts. Don't reset the "route to SP" bit (4).
>
> I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
> SP-based keyboard for me and d
On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
and 72 interrupts. Don't reset the "route to SP" bit (4).
I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
SP-based keyboard for me and defines
ICU_INT_ROUTE_SP_IRQ to be 1 << 4. When asked for a data she
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