Re: [PATCH v4 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq

2014-09-01 Thread Mike Turquette
Quoting Tuomas Tynkkynen (2014-08-20 14:04:28) > v4 changes: > DFLL: > - fix wrong register accessors used for the DFLL_OUTPUT_CFG register > - I decided to leave the dfll_i2c_{readl,writel} separate since the > correct barrier function still needs to be called > - fix PMI

[PATCH v4 00/16] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq

2014-08-20 Thread Tuomas Tynkkynen
v4 changes: DFLL: - fix wrong register accessors used for the DFLL_OUTPUT_CFG register - I decided to leave the dfll_i2c_{readl,writel} separate since the correct barrier function still needs to be called - fix PMIC I2C voltage register address being uninitialized cpufreq: