On 2021-01-15 04:01, Samuel Holland wrote:
Hello,
On 1/14/21 3:06 PM, Marc Zyngier wrote:
Hi Samuel,
On 2021-01-12 05:59, Samuel Holland wrote:
[...]
+static void sun6i_r_intc_ack_nmi(void)
+{
+ writel(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
writel_relaxed()
Hello,
On 1/14/21 3:06 PM, Marc Zyngier wrote:
> Hi Samuel,
>
> On 2021-01-12 05:59, Samuel Holland wrote:
>
> [...]
>
>> +static void sun6i_r_intc_ack_nmi(void)
>> +{
>> +writel(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
>
> writel_relaxed()
irq_chip_unmask_parent(), which calls
Hi Samuel,
On 2021-01-12 05:59, Samuel Holland wrote:
[...]
> +static void sun6i_r_intc_ack_nmi(void)
> +{
> + writel(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
writel_relaxed()
> +}
> +
> +static void sun6i_r_intc_nmi_ack(struct irq_data *data)
> +{
> + if
The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
- To control the trigger, latch, and mask for the NMI input pin
- To provide the interrupt input for the ARISC
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