On Wed, 7 Jun 2017 16:21:15 +0900
Masahiro Yamada wrote:
> Hi Boris,
>
>
> 2017-06-07 16:02 GMT+09:00 Boris Brezillon
> :
> > On Wed, 7 Jun 2017 12:09:31 +0900
> > Masahiro Yamada wrote:
> >
> >> >> +
> >> >> +static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip
> >> >> *chip
Hi Boris,
2017-06-07 16:02 GMT+09:00 Boris Brezillon :
> On Wed, 7 Jun 2017 12:09:31 +0900
> Masahiro Yamada wrote:
>
>> >> +
>> >> +static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
>> >> + struct denali_nand_info *denali)
>> >> +{
>> >> + str
On Wed, 7 Jun 2017 12:09:31 +0900
Masahiro Yamada wrote:
> >> +
> >> +static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
> >> + struct denali_nand_info *denali)
> >> +{
> >> + struct nand_ecc_caps caps;
> >> + int ret;
> >> +
> >> + caps.
Hi Boris,
2017-06-07 7:01 GMT+09:00 Boris Brezillon :
> On Tue, 6 Jun 2017 08:21:43 +0900
> Masahiro Yamada wrote:
>
>> This driver was originally written for the Intel MRST platform with
>> several platform-specific parameters hard-coded.
>>
>> Currently, the ECC settings are hard-coded as fol
On Tue, 6 Jun 2017 08:21:43 +0900
Masahiro Yamada wrote:
> This driver was originally written for the Intel MRST platform with
> several platform-specific parameters hard-coded.
>
> Currently, the ECC settings are hard-coded as follows:
>
> #define ECC_SECTOR_SIZE 512
> #define ECC_8BITS
This driver was originally written for the Intel MRST platform with
several platform-specific parameters hard-coded.
Currently, the ECC settings are hard-coded as follows:
#define ECC_SECTOR_SIZE 512
#define ECC_8BITS 14
#define ECC_15BITS 26
Therefore, the driver can only suppo
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