Re: [PATCH v4 1/2] perf: riscv: preliminary RISC-V support

On Thu, Apr 19, 2018 at 12:46:24PM -0700, Atish Patra wrote: > On 4/17/18 7:13 PM, Alan Kao wrote: > >This patch provide a basic PMU, riscv_base_pmu, which supports two > >general hardware event, instructions and cycles. Furthermore, this > >PMU serves as a reference implementation to ease the por

Re: [PATCH v4 1/2] perf: riscv: preliminary RISC-V support

On 4/17/18 7:13 PM, Alan Kao wrote: This patch provide a basic PMU, riscv_base_pmu, which supports two general hardware event, instructions and cycles. Furthermore, this PMU serves as a reference implementation to ease the portings in the future. riscv_base_pmu should be able to run on any RISC

[PATCH v4 1/2] perf: riscv: preliminary RISC-V support

This patch provide a basic PMU, riscv_base_pmu, which supports two general hardware event, instructions and cycles. Furthermore, this PMU serves as a reference implementation to ease the portings in the future. riscv_base_pmu should be able to run on any RISC-V machine that conforms to the Priv-S