Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

On 05/12/14 13:34, Javier Martinez Canillas wrote: > Hello Sylwester, > > On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote: >>> >> Tested-by: Javier Martinez Canillas >> > >> > Can you confirm sound works with this patch on exynos5420 ? Or does >> > your Tested-by refer only to successful

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Hi Krzysztof, On 05/12/14 12:00, Krzysztof Kozlowski wrote: > Audio subsystem clocks are located in separate block. If clock for this > block (from main clock domain) 'mau_epll' is gated then any read or > write to audss registers will block. > > This was observed on Exynos 5420 platforms

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Hello Sylwester, On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote: >> Tested-by: Javier Martinez Canillas > > Can you confirm sound works with this patch on exynos5420 ? Or does > your Tested-by refer only to successful booting ? > I tested latest linux-next + "clk: samsung: Fix double add of

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Javier, On 05/12/14 12:00, Krzysztof Kozlowski wrote: > Audio subsystem clocks are located in separate block. If clock for this > block (from main clock domain) 'mau_epll' is gated then any read or > write to audss registers will block. > > This was observed on Exynos 5420 platforms (Arndale

[PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Audio subsystem clocks are located in separate block. If clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This was observed on Exynos 5420 platforms (Arndale Octa and Peach Pi/Pit) after introducing runtime PM to pl330 DMA

[PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Audio subsystem clocks are located in separate block. If clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This was observed on Exynos 5420 platforms (Arndale Octa and Peach Pi/Pit) after introducing runtime PM to pl330 DMA

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Javier, On 05/12/14 12:00, Krzysztof Kozlowski wrote: Audio subsystem clocks are located in separate block. If clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This was observed on Exynos 5420 platforms (Arndale Octa and

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Hello Sylwester, On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Can you confirm sound works with this patch on exynos5420 ? Or does your Tested-by refer only to successful booting ? I tested latest linux-next + clk:

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

Hi Krzysztof, On 05/12/14 12:00, Krzysztof Kozlowski wrote: Audio subsystem clocks are located in separate block. If clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This was observed on Exynos 5420 platforms (Arndale

Re: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

On 05/12/14 13:34, Javier Martinez Canillas wrote: Hello Sylwester, On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Can you confirm sound works with this patch on exynos5420 ? Or does your Tested-by refer only to