Declare sync_task_ctx() methods at the generic and x86 specific
pmu types to bridge calls to platform specific pmu code on optimized
context switch path between equivalent task perf event contexts.
Signed-off-by: Alexey Budankov <alexey.budan...@linux.intel.com>
---
Changes in v4:
- marked sync_task_ctx() as the optional in code comments;
- renamed params of sync_task_ctx() to prev and next;
---
arch/x86/events/perf_event.h | 8 ++++++++
include/linux/perf_event.h | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index ecacfbf4ebc1..be78f2765f74 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -682,6 +682,14 @@ struct x86_pmu {
*/
atomic_t lbr_exclusive[x86_lbr_exclusive_max];
+ /*
+ * perf task context (i.e. struct perf_event_context::task_ctx_data)
switch helper
+ * to bridge calls from perf/core to perf/x86. See struct
pmu::sync_task_ctx() usage
+ * for examples;
+ */
+ void (*sync_task_ctx)(struct x86_perf_task_context *prev,
+ struct x86_perf_task_context *next);
+
/*
* AMD bits
*/
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 587ae4d002f5..4b96b4a5ac03 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -410,6 +410,13 @@ struct pmu {
*/
size_t task_ctx_size;
+ /*
+ * PMU specific parts of task perf event context (i.e.
ctx->task_ctx_data)
+ * can be synchronized using this function. See Intel LBR callstack
support
+ * implementation and Perf core context switch handling callbacks for
usage
+ * examples.
+ */
+ void (*sync_task_ctx) (void *prev, void *next); /* optional */
/*
* Set up pmu-private data structures for an AUX area
--
2.20.1
