Fenghua,
On Wed, Jan 27 2021 at 22:39, Fenghua Yu wrote:
>> On Wed, Jan 27, 2021 2:16 PM, Thomas Gleixner wrote:
>> On Tue, Nov 24 2020 at 20:52, Fenghua Yu wrote:
>>
>> > A bus lock is acquired though either split locked access to writeback
>> > (WB) memory or any locked access to non-WB
Hi, Thomas,
> On Wed, Jan 27, 2021 2:16 PM, Thomas Gleixner wrote:
> On Tue, Nov 24 2020 at 20:52, Fenghua Yu wrote:
>
> > A bus lock is acquired though either split locked access to writeback
> > (WB) memory or any locked access to non-WB memory. This is typically
> > >1000 cycles slower than
On Tue, Nov 24 2020 at 20:52, Fenghua Yu wrote:
> A bus lock is acquired though either split locked access to
> writeback (WB) memory or any locked access to non-WB memory. This is
> typically >1000 cycles slower than an atomic operation within a cache
> line. It also disrupts performance on
A bus lock is acquired though either split locked access to
writeback (WB) memory or any locked access to non-WB memory. This is
typically >1000 cycles slower than an atomic operation within a cache
line. It also disrupts performance on other cores.
Some CPUs have ability to notify the kernel by
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