Add OPP tables required to scale DDR/L3 per freq-domain on SC7180 SoCs. Signed-off-by: Sibi Sankar <si...@codeaurora.org> ---
v4: https://lore.kernel.org/patchwork/cover/1230626/ * Reworked based on Georgi's bindings arch/arm64/boot/dts/qcom/sc7180.dtsi | 168 +++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4216b574c0803..2421b7bb7dd83 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,gpucc-sc7180.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sc7180.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc7180.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> @@ -100,6 +101,10 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -123,6 +128,10 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { @@ -142,6 +151,10 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { @@ -161,6 +174,10 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { @@ -180,6 +197,10 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { @@ -199,6 +220,10 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { @@ -218,6 +243,10 @@ &BIG_CPU_SLEEP_1 capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { @@ -237,6 +266,10 @@ &BIG_CPU_SLEEP_1 capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { @@ -336,6 +369,141 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu0_opp2: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu0_opp3: opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu0_opp4: opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <1804000 8908800>; + }; + + cpu0_opp5: opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <2188000 12902400>; + }; + + cpu0_opp6: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 12902400>; + }; + + cpu0_opp7: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 15052800>; + }; + + cpu0_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <3072000 15052800>; + }; + + cpu0_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <3072000 15052800>; + }; + + cpu0_opp10: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <4068000 22425600>; + }; + }; + + cpu6_opp_table: cpu6_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp2: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp3: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp4: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp5: opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp6: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <4068000 12902400>; + }; + + cpu6_opp7: opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu6_opp8: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu6_opp9: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu6_opp10: opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <6220000 22425600>; + }; + + cpu6_opp11: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <6220000 22425600>; + }; + + cpu6_opp12: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 22425600>; + }; + + cpu6_opp13: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu6_opp14: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu6_opp15: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 23347200>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
