Add MT8192 camsys rawb clock provider Signed-off-by: Weiyi Lu <weiyi...@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-cam_rawb.c | 59 ++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawb.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 230e3f7..34b3a52 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -467,6 +467,12 @@ config COMMON_CLK_MT8192_CAMSYS_RAWA help This driver supports MediaTek MT8192 camsys_rawa clocks. +config COMMON_CLK_MT8192_CAMSYS_RAWB + bool "Clock driver for MediaTek MT8192 camsys_rawb" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 camsys_rawb clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index cf1ec78..a0bcb00 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -65,5 +65,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWA) += clk-mt8192-cam_rawa.o +obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWB) += clk-mt8192-cam_rawb.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-cam_rawb.c b/drivers/clk/mediatek/clk-mt8192-cam_rawb.c new file mode 100644 index 0000000..b3855f7 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-cam_rawb.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi...@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs cam_rawb_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM_RAWB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &cam_rawb_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate cam_rawb_clks[] = { + GATE_CAM_RAWB(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "cam_sel", 0), + GATE_CAM_RAWB(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "cam_sel", 1), + GATE_CAM_RAWB(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "cam_sel", 2), +}; + +static int clk_mt8192_cam_rawb_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(CLK_CAM_RAWB_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, cam_rawb_clks, ARRAY_SIZE(cam_rawb_clks), clk_data); + if (r) + return r; + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} + +static const struct of_device_id of_match_clk_mt8192_cam_rawb[] = { + { .compatible = "mediatek,mt8192-camsys_rawb", }, + {} +}; + +static struct platform_driver clk_mt8192_cam_rawb_drv = { + .probe = clk_mt8192_cam_rawb_probe, + .driver = { + .name = "clk-mt8192-cam_rawb", + .of_match_table = of_match_clk_mt8192_cam_rawb, + }, +}; + +builtin_platform_driver(clk_mt8192_cam_rawb_drv); -- 1.8.1.1.dirty