On Fri, 2019-03-08 at 08:54 +0100, Paolo Bonzini wrote:
> On 08/03/19 07:10, Xiaoyao Li wrote:
> > > so that non-virtualizable features are hidden and
> > >
> > > if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
> > > data |= CORE_CAP_SPLIT_LOCK_DETECT;
> > >
> > > so that userspace
On 08/03/19 07:10, Xiaoyao Li wrote:
>> so that non-virtualizable features are hidden and
>>
>> if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
>> data |= CORE_CAP_SPLIT_LOCK_DETECT;
>>
>> so that userspace gets "for free" the FMS list that will be added
>> later to the kernel.
Hi, Paolo
On Mon, 2019-03-04 at 09:42 +0100, Paolo Bonzini wrote:
> On 02/03/19 03:45, Fenghua Yu wrote:
> > From: Xiaoyao Li
> >
> > MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, bit 5 of which
> > reports the capability of enabling detection of split locks (will be
> > supported on
On Mon, 2019-03-04 at 09:42 +0100, Paolo Bonzini wrote:
> On 02/03/19 03:45, Fenghua Yu wrote:
> > From: Xiaoyao Li
> >
> > MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, bit 5 of which
> > reports the capability of enabling detection of split locks (will be
> > supported on future
On 02/03/19 03:45, Fenghua Yu wrote:
> From: Xiaoyao Li
>
> MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, bit 5 of which
> reports the capability of enabling detection of split locks (will be
> supported on future processors based on Tremont microarchitecture and
> later).
>
> Please
From: Xiaoyao Li
MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, bit 5 of which
reports the capability of enabling detection of split locks (will be
supported on future processors based on Tremont microarchitecture and
later).
Please check the latest Intel Architecture Instruction Set
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