Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote: > On 4/12/2018 10:30 PM, Sinan Kaya wrote: > > + /* prevent prefetching of coherent DMA dma prematurely */ \ > > I tried to write DMA data but my keyboard is not cooperating. I'll hold onto > posting another version until I hear b

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

On 4/12/2018 10:30 PM, Sinan Kaya wrote: > + /* prevent prefetching of coherent DMA dma prematurely */ \ I tried to write DMA data but my keyboard is not cooperating. I'll hold onto posting another version until I hear back from you for wmb(). -- Sinan Kaya Qualcomm Datacenter Technolo

[PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

While a barrier is present in writeX() function before the register write, a similar barrier is missing in the readX() function after the register read. This could allow memory accesses following readX() to observe stale data. Signed-off-by: Sinan Kaya Reported-by: Arnd Bergmann --- arch/mips/i