Hi Lorenzo,
On 4/3/2019 4:31 AM, Lorenzo Pieralisi wrote:
> On Wed, Apr 03, 2019 at 08:41:44AM +0530, Srinath Mannam wrote:
>> Hi Lorenzo,
>>
>> Please see my reply below,
>>
>> On Tue, Apr 2, 2019 at 7:08 PM Lorenzo Pieralisi
>> wrote:
>>>
>>> On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Ma
Hi Lorenzo,
I am sorry, I took your long time. In my commit log I gave details
about purpose of feature instead of implementation.
Thanks a lot for all inputs and knowledge. I will remember and follow
these notes while writing commit log.
commit log re-written by you is very much impressive and ha
On Wed, Apr 03, 2019 at 08:41:44AM +0530, Srinath Mannam wrote:
> Hi Lorenzo,
>
> Please see my reply below,
>
> On Tue, Apr 2, 2019 at 7:08 PM Lorenzo Pieralisi
> wrote:
> >
> > On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Mannam wrote:
> >
> > [...]
> >
> > > > Ok - I start to understand.
Hi Lorenzo,
Please see my reply below,
On Tue, Apr 2, 2019 at 7:08 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Mannam wrote:
>
> [...]
>
> > > Ok - I start to understand. What does it mean in HW terms that your
> > > 32bit AXI address region size is 32MB ? P
On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Mannam wrote:
[...]
> > Ok - I start to understand. What does it mean in HW terms that your
> > 32bit AXI address region size is 32MB ? Please explain to me in details.
> >
> In our PCIe controller HW, AXI address from 0x4200 to 0x4400
> o
Hi Lorenzo,
Please see my reply below,
On Tue, Apr 2, 2019 at 3:56 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Apr 02, 2019 at 03:20:21PM +0530, Srinath Mannam wrote:
> > Hi Ray,
> >
> > Thanks for detailed explanation.
> > Please see some more details below.
> >
> > On Tue, Apr 2, 2019 at 3:33 AM R
On Tue, Apr 02, 2019 at 03:20:21PM +0530, Srinath Mannam wrote:
> Hi Ray,
>
> Thanks for detailed explanation.
> Please see some more details below.
>
> On Tue, Apr 2, 2019 at 3:33 AM Ray Jui wrote:
> >
> > Hi Lorenzo/Srinath,
> >
> > I look at the commit message again and indeed it looks quite
Hi Ray,
Thanks for detailed explanation.
Please see some more details below.
On Tue, Apr 2, 2019 at 3:33 AM Ray Jui wrote:
>
> Hi Lorenzo/Srinath,
>
> I look at the commit message again and indeed it looks quite confusing.
>
> I'll add my comment inline in the code section. I hope that will help
Hi Lorenzo/Srinath,
I look at the commit message again and indeed it looks quite confusing.
I'll add my comment inline in the code section. I hope that will help to
make it more clear.
On 4/1/2019 9:44 AM, Lorenzo Pieralisi wrote:
> On Mon, Apr 01, 2019 at 11:04:48AM +0530, Srinath Mannam wrote:
On Mon, Apr 01, 2019 at 11:04:48AM +0530, Srinath Mannam wrote:
> Hi Lorenzo,
>
> Please see my reply below,
>
> On Fri, Mar 29, 2019 at 11:06 PM Lorenzo Pieralisi
> wrote:
> >
> > On Fri, Mar 01, 2019 at 10:22:16AM +0530, Srinath Mannam wrote:
> > > In the present driver outbound window configu
Hi Lorenzo,
Please see my reply below,
On Fri, Mar 29, 2019 at 11:06 PM Lorenzo Pieralisi
wrote:
>
> On Fri, Mar 01, 2019 at 10:22:16AM +0530, Srinath Mannam wrote:
> > In the present driver outbound window configuration is done to map above
> > 32-bit address I/O regions with corresponding PCI
On Fri, Mar 01, 2019 at 10:22:16AM +0530, Srinath Mannam wrote:
> In the present driver outbound window configuration is done to map above
> 32-bit address I/O regions with corresponding PCI memory range given in
> ranges DT property.
>
> This patch add outbound window configuration to map below 3
In the present driver outbound window configuration is done to map above
32-bit address I/O regions with corresponding PCI memory range given in
ranges DT property.
This patch add outbound window configuration to map below 32-bit I/O range
with corresponding PCI memory, which helps to access I/O r
13 matches
Mail list logo
