On 04/06, Rick Altherr wrote:
> On Wed, Apr 5, 2017 at 6:10 PM, Stephen Boyd wrote:
> > On 04/05, Rick Altherr wrote:
> >> On Wed, Apr 5, 2017 at 1:27 PM, Stephen Boyd wrote:
> >> > On 03/23, Rick Altherr wrote:
> >> >> +
> >> >> +static int aspeed_adc_probe(struct platform_device *pdev)
> >> >>
On Wed, Apr 5, 2017 at 6:10 PM, Stephen Boyd wrote:
> On 04/05, Rick Altherr wrote:
>> On Wed, Apr 5, 2017 at 1:27 PM, Stephen Boyd wrote:
>> > On 03/23, Rick Altherr wrote:
>> >> +
>> >> +static int aspeed_adc_probe(struct platform_device *pdev)
>> >> +{
>> >> + struct iio_dev *indio_dev;
>>
On 04/05, Rick Altherr wrote:
> On Wed, Apr 5, 2017 at 1:27 PM, Stephen Boyd wrote:
> > On 03/23, Rick Altherr wrote:
> >> +
> >> +static int aspeed_adc_probe(struct platform_device *pdev)
> >> +{
> >> + struct iio_dev *indio_dev;
> >> + struct aspeed_adc_data *data;
> >> + const struc
On Wed, Apr 5, 2017 at 1:27 PM, Stephen Boyd wrote:
> On 03/23, Rick Altherr wrote:
>> +
>> +static int aspeed_adc_probe(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev;
>> + struct aspeed_adc_data *data;
>> + const struct aspeed_adc_model_data *model_data;
>> +
On 03/23, Rick Altherr wrote:
> +
> +static int aspeed_adc_probe(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev;
> + struct aspeed_adc_data *data;
> + const struct aspeed_adc_model_data *model_data;
> + struct resource *res;
> + const char *clk_parent_name;
> +
On Sat, Mar 25, 2017 at 10:32 AM, Jonathan Cameron wrote:
> On 23/03/17 18:41, Rick Altherr wrote:
>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>> interrupts are supported by the hardware but are not currently implemented.
>>
>> Signed-off-by: Rick Altherr
> Nice li
On 23/03/17 18:41, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr
Nice little driver.
I'd like input from clk maintainers on the clk stuff
On Fri, Mar 24, 2017 at 5:11 AM, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr
I gave it another test with the hwmon bridge on my ast2500
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: Rick Altherr
---
Changes in v4:
- Avoid copying per-model data to per-instance data
Changes in v3:
- Drop model numbers from descri
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