Re: [PATCH v4 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

2019-01-23 Thread Vignesh R
On 23-Jan-19 2:15 PM, Boris Brezillon wrote: > On Tue, 22 Jan 2019 12:11:37 +0530 > Vignesh R wrote: > >> Cadence OSPI controller IP supports Octal IO (x8 IO lines), >> It also has an integrated PHY. IP register layout is very >> similar to existing QSPI IP except for additional bits to

Re: [PATCH v4 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

2019-01-23 Thread Boris Brezillon
On Tue, 22 Jan 2019 12:11:37 +0530 Vignesh R wrote: > Cadence OSPI controller IP supports Octal IO (x8 IO lines), > It also has an integrated PHY. IP register layout is very > similar to existing QSPI IP except for additional bits to support Octal > and Octal DDR mode. Therefore, extend current

Re: [PATCH v4 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

2019-01-22 Thread Tudor.Ambarus
On 01/22/2019 08:41 AM, Vignesh R wrote: > Cadence OSPI controller IP supports Octal IO (x8 IO lines), > It also has an integrated PHY. IP register layout is very > similar to existing QSPI IP except for additional bits to support Octal > and Octal DDR mode. Therefore, extend current driver to

[PATCH v4 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

2019-01-21 Thread Vignesh R
Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Only Octal SDR read (1-1-8)mode