Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-27 Thread Linus Walleij
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery wrote: > The System Control Unit IP block in the Aspeed SoCs is typically where > the pinmux configuration is found, but not always. A number of pins > depend on state in one of LPC Host Control (LHC) or SoC Display > Controller

Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-27 Thread Linus Walleij
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery wrote: > The System Control Unit IP block in the Aspeed SoCs is typically where > the pinmux configuration is found, but not always. A number of pins > depend on state in one of LPC Host Control (LHC) or SoC Display > Controller (GFX) IP blocks, so

Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-22 Thread Rob Herring
On Tue, Dec 20, 2016 at 06:05:48PM +1030, Andrew Jeffery wrote: > The System Control Unit IP block in the Aspeed SoCs is typically where > the pinmux configuration is found, but not always. A number of pins > depend on state in one of LPC Host Control (LHC) or SoC Display > Controller (GFX) IP

Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-22 Thread Rob Herring
On Tue, Dec 20, 2016 at 06:05:48PM +1030, Andrew Jeffery wrote: > The System Control Unit IP block in the Aspeed SoCs is typically where > the pinmux configuration is found, but not always. A number of pins > depend on state in one of LPC Host Control (LHC) or SoC Display > Controller (GFX) IP

[PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-19 Thread Andrew Jeffery
The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these

[PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-19 Thread Andrew Jeffery
The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these