On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote:
>
> On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
> > Add driver code for the SiFive FU740 PRCI IP block. This IP block
> > handles reset and clock control for the SiFive FU740 device and
> > implements SoC-level clock tre
On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote:
>
> On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
> > Add driver code for the SiFive FU740 PRCI IP block. This IP block
> > handles reset and clock control for the SiFive FU740 device and
> > implements SoC-level clock tre
On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contribu
On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contribu
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Signed-off-by: Z
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