Re: [PATCH v4 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

2017-08-16 Thread Zhangshaokun
Hi Mark, On 2017/8/15 18:41, Mark Rutland wrote: > On Tue, Jul 25, 2017 at 08:10:39PM +0800, Shaokun Zhang wrote: >> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each >> L3C has own control, counter and interrupt registers and is an separate >> PMU. For each L3C PMU, it has 8-

Re: [PATCH v4 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

2017-08-15 Thread Mark Rutland
On Tue, Jul 25, 2017 at 08:10:39PM +0800, Shaokun Zhang wrote: > This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each > L3C has own control, counter and interrupt registers and is an separate > PMU. For each L3C PMU, it has 8-programable counters and supports 0x60 > events, event

[PATCH v4 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

2017-07-25 Thread Shaokun Zhang
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each L3C has own control, counter and interrupt registers and is an separate PMU. For each L3C PMU, it has 8-programable counters and supports 0x60 events, event code is 8-bits and every counter is free-running. Interrupt is supporte