Re: [PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

2014-10-03 Thread Mark Brown
On Fri, Oct 03, 2014 at 04:18:56PM +0300, Dmitry Lavnikevich wrote: > Current caching implementation during regcache_sync() call bypasses > all register writes of values that are already known as default > (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5 Applied, thanks. This sho

[PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

2014-10-03 Thread Dmitry Lavnikevich
Current caching implementation during regcache_sync() call bypasses all register writes of values that are already known as default (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5 (AIC3X_PLL_PROGC_REG) write should be immediately followed by register 6 write (AIC3X_PLL_PROGD_REG)