Re: [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift

On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote: > > On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong...@sifive.com wrote: > > The clk enable bit should be 31 instead of 24. > > > > Signed-off-by: Zong Li > > Reported-by: Pragnesh Patel > > --- > > drivers/clk/sifive/sifive-prci.h | 4 ++-- >

Re: [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift

On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong...@sifive.com wrote: The clk enable bit should be 31 instead of 24. Signed-off-by: Zong Li Reported-by: Pragnesh Patel --- drivers/clk/sifive/sifive-prci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sifive

[PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift

The clk enable bit should be 31 instead of 24. Signed-off-by: Zong Li Reported-by: Pragnesh Patel --- drivers/clk/sifive/sifive-prci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 802fc8fb9c09..