Around Wed 29 Jul 2015 17:09:59 +0200 or thereabout, Nicolas Ferre wrote:
> Le 29/07/2015 16:51, Andy Shevchenko a écrit :
>> On Thu, Jul 2, 2015 at 4:18 PM, Cyrille Pitchen
>> wrote:
>>> Depending on the hardware, TX and RX FIFOs may be available. The RX
>>> FIFO can avoid receive overruns,
Hi Andy,
On 29/07/2015 at 17:51:38 +0300, Andy Shevchenko wrote :
> On Thu, Jul 2, 2015 at 4:18 PM, Cyrille Pitchen
> wrote:
> > Depending on the hardware, TX and RX FIFOs may be available. The RX
> > FIFO can avoid receive overruns, especially when DMA transfers are
> > not used to read data
On Thu, Jul 2, 2015 at 4:18 PM, Cyrille Pitchen
wrote:
> Depending on the hardware, TX and RX FIFOs may be available. The RX
> FIFO can avoid receive overruns, especially when DMA transfers are
> not used to read data from the Receive Holding Register. For heavy
> system load, The CPU is likely
Around Wed 29 Jul 2015 17:09:59 +0200 or thereabout, Nicolas Ferre wrote:
Le 29/07/2015 16:51, Andy Shevchenko a écrit :
On Thu, Jul 2, 2015 at 4:18 PM, Cyrille Pitchen
cyrille.pitc...@atmel.com wrote:
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive
On Thu, Jul 2, 2015 at 4:18 PM, Cyrille Pitchen
cyrille.pitc...@atmel.com wrote:
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive overruns, especially when DMA transfers are
not used to read data from the Receive Holding Register. For heavy
system
Hi Andy,
On 29/07/2015 at 17:51:38 +0300, Andy Shevchenko wrote :
On Thu, Jul 2, 2015 at 4:18 PM, Cyrille Pitchen
cyrille.pitc...@atmel.com wrote:
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive overruns, especially when DMA transfers are
not
Le 02/07/2015 15:18, Cyrille Pitchen a écrit :
> Depending on the hardware, TX and RX FIFOs may be available. The RX
> FIFO can avoid receive overruns, especially when DMA transfers are
> not used to read data from the Receive Holding Register. For heavy
> system load, The CPU is likely not be
Le 02/07/2015 15:18, Cyrille Pitchen a écrit :
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive overruns, especially when DMA transfers are
not used to read data from the Receive Holding Register. For heavy
system load, The CPU is likely not be able to
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive overruns, especially when DMA transfers are
not used to read data from the Receive Holding Register. For heavy
system load, The CPU is likely not be able to fetch data fast enough
from the RHR.
In addition,
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive overruns, especially when DMA transfers are
not used to read data from the Receive Holding Register. For heavy
system load, The CPU is likely not be able to fetch data fast enough
from the RHR.
In addition,
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