On 12.06.2018 10:13, Boris Brezillon wrote:
> On Tue, 12 Jun 2018 10:02:12 +0200
> Stefan Agner wrote:
>
>> >> +static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
>> >> + struct nand_chip *chip,
>> >> + uint8_t *buf, int oob_req
On Tue, 12 Jun 2018 15:24:41 -0600
Jens Axboe wrote:
> On 6/12/18 2:20 PM, Stefan Agner wrote:
> > On 12.06.2018 17:24, Jens Axboe wrote:
> >> On 6/12/18 3:17 AM, Stefan Agner wrote:
> >>> [also added Jens Axboe]
> >>>
> >>> On 12.06.2018 10:27, Boris Brezillon wrote:
> On Tue, 12 Jun
On 6/12/18 2:20 PM, Stefan Agner wrote:
> On 12.06.2018 17:24, Jens Axboe wrote:
>> On 6/12/18 3:17 AM, Stefan Agner wrote:
>>> [also added Jens Axboe]
>>>
>>> On 12.06.2018 10:27, Boris Brezillon wrote:
On Tue, 12 Jun 2018 10:06:42 +0200
Stefan Agner wrote:
> On 12.06.2018 02:0
On Tue, 12 Jun 2018 22:20:58 +0200
Stefan Agner wrote:
> On 12.06.2018 17:24, Jens Axboe wrote:
> > On 6/12/18 3:17 AM, Stefan Agner wrote:
> >> [also added Jens Axboe]
> >>
> >> On 12.06.2018 10:27, Boris Brezillon wrote:
> >>> On Tue, 12 Jun 2018 10:06:42 +0200
> >>> Stefan Agner wrote:
>
On 12.06.2018 17:24, Jens Axboe wrote:
> On 6/12/18 3:17 AM, Stefan Agner wrote:
>> [also added Jens Axboe]
>>
>> On 12.06.2018 10:27, Boris Brezillon wrote:
>>> On Tue, 12 Jun 2018 10:06:42 +0200
>>> Stefan Agner wrote:
>>>
On 12.06.2018 02:03, Dmitry Osipenko wrote:
> On Monday, 11 June
On 6/12/18 3:17 AM, Stefan Agner wrote:
> [also added Jens Axboe]
>
> On 12.06.2018 10:27, Boris Brezillon wrote:
>> On Tue, 12 Jun 2018 10:06:42 +0200
>> Stefan Agner wrote:
>>
>>> On 12.06.2018 02:03, Dmitry Osipenko wrote:
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC mak
On Tue, 12 Jun 2018 11:17:09 +0200
Stefan Agner wrote:
> [also added Jens Axboe]
>
> On 12.06.2018 10:27, Boris Brezillon wrote:
> > On Tue, 12 Jun 2018 10:06:42 +0200
> > Stefan Agner wrote:
> >
> >> On 12.06.2018 02:03, Dmitry Osipenko wrote:
> >> > On Monday, 11 June 2018 23:52:22 MSK S
[also added Jens Axboe]
On 12.06.2018 10:27, Boris Brezillon wrote:
> On Tue, 12 Jun 2018 10:06:42 +0200
> Stefan Agner wrote:
>
>> On 12.06.2018 02:03, Dmitry Osipenko wrote:
>> > On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>> >> Add support for the NAND flash controller found on N
On Tue, 12 Jun 2018 10:06:42 +0200
Stefan Agner wrote:
> On 12.06.2018 02:03, Dmitry Osipenko wrote:
> > On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> >> Add support for the NAND flash controller found on NVIDIA
> >> Tegra 2 SoCs. This implementation does not make use of the
> >> c
On Tue, 12 Jun 2018 10:02:12 +0200
Stefan Agner wrote:
> >> +static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
> >> +struct nand_chip *chip,
> >> +uint8_t *buf, int oob_required, int page)
> >> +{
> >> + struct tegra_nand_
On 12.06.2018 02:03, Dmitry Osipenko wrote:
> On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done i
On 12.06.2018 01:32, Dmitry Osipenko wrote:
> On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done i
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC mak
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC mak
Hi Stefan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on mtd/nand/next]
[also build test WARNING on v4.17 next-20180608]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/co
Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.
Signed-off-by: Lucas Stach
17 matches
Mail list logo
