Re: [PATCH v4 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

2017-08-16 Thread Zhangshaokun
Hi Mark, On 2017/8/15 19:05, Mark Rutland wrote: > On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote: >> +/* HHA register definition */ >> +#define HHA_INT_MASK0x0804 >> +#define HHA_INT_STATUS 0x0808 >> +#define HHA_INT_CLEAR 0x080C >> +#defi

Re: [PATCH v4 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

2017-08-15 Thread Mark Rutland
On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote: > +/* HHA register definition */ > +#define HHA_INT_MASK 0x0804 > +#define HHA_INT_STATUS 0x0808 > +#define HHA_INT_CLEAR0x080C > +#define HHA_PERF_CTRL0x1E00 > +#define HHA_EVENT_CT

[PATCH v4 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

2017-07-25 Thread Shaokun Zhang
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon SoC. This patch adds support for HHA PMU driver, Each HHA has own control, counter and interrupt registers and is an separate PMU. For each HHA PMU, it has 16-programable counters and supports 0x50 events, event code is 8-bits