Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On mer., avril 26 2017, Linus Walleij wrote: > On Wed, Apr 26, 2017 at 11:23 AM, Gregory CLEMENT > wrote: >> On lun., avril 24 2017, Linus Walleij wrote: > +

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On mer., avril 26 2017, Linus Walleij wrote: > On Wed, Apr 26, 2017 at 11:23 AM, Gregory CLEMENT > wrote: >> On lun., avril 24 2017, Linus Walleij wrote: > + spin_lock_irqsave(>irq_lock, flags); + status = readl_relaxed(info->base +

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

On Wed, Apr 26, 2017 at 11:23 AM, Gregory CLEMENT wrote: > On lun., avril 24 2017, Linus Walleij wrote: >>> + spin_lock_irqsave(>irq_lock, flags); >>> + status = readl_relaxed(info->base + IRQ_STATUS + 4

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

On Wed, Apr 26, 2017 at 11:23 AM, Gregory CLEMENT wrote: > On lun., avril 24 2017, Linus Walleij wrote: >>> + spin_lock_irqsave(>irq_lock, flags); >>> + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); >>> + /* Manage only the interrupt that

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On lun., avril 24 2017, Linus Walleij wrote: > On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT > wrote: > >> The Armada 37xx SoCs can handle interrupt through GPIO. However it can >> only manage the edge ones. >> >> The

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On lun., avril 24 2017, Linus Walleij wrote: > On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT > wrote: > >> The Armada 37xx SoCs can handle interrupt through GPIO. However it can >> only manage the edge ones. >> >> The way the interrupt are managed are classical so we can use the

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

So I touched something in gmail and it shot off the mail prematurely. My apologies. But my review was done anyways. Yours, Linus Walleij

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

So I touched something in gmail and it shot off the mail prematurely. My apologies. But my review was done anyways. Yours, Linus Walleij

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can > only manage the edge ones. > > The way the interrupt are managed are classical so we can use the generic > interrupt chip model. >

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can > only manage the edge ones. > > The way the interrupt are managed are classical so we can use the generic > interrupt chip model. > > The only unusual "feature" is

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

Argh, I sill have the typo in the title of this patch! :( If you are going to apply it could you fix it, else it will be fixed in the next version. Sorry, Gregory On mer., avril 05 2017, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle

Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

Argh, I sill have the typo in the title of this patch! :( If you are going to apply it could you fix it, else it will be fixed in the next version. Sorry, Gregory On mer., avril 05 2017, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can >

[PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed are classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller.

[PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support

The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed are classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller.