Re: [PATCH v4 6/7] arm64: mm: Implement 4 levels of translation tables

2014-04-29 Thread Jungseok Lee
On Wednesday, April 30, 2014 2:04 AM, Catalin Marinas wrote: > On Tue, Apr 29, 2014 at 05:59:33AM +0100, Jungseok Lee wrote: > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index > > 0fd5650..03ec424 100644 > > --- a/arch/arm64/kernel/head.S > > +++ b/arch/arm64/kernel/head.S

Re: [PATCH v4 6/7] arm64: mm: Implement 4 levels of translation tables

2014-04-29 Thread Catalin Marinas
On Tue, Apr 29, 2014 at 05:59:33AM +0100, Jungseok Lee wrote: > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index 0fd5650..03ec424 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -37,8 +37,9 @@ > > /* > * swapper_pg_dir is the virtual

Re: [PATCH v4 6/7] arm64: mm: Implement 4 levels of translation tables

2014-04-29 Thread Catalin Marinas
On Tue, Apr 29, 2014 at 05:59:33AM +0100, Jungseok Lee wrote: diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 0fd5650..03ec424 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -37,8 +37,9 @@ /* * swapper_pg_dir is the virtual address of the

Re: [PATCH v4 6/7] arm64: mm: Implement 4 levels of translation tables

2014-04-29 Thread Jungseok Lee
On Wednesday, April 30, 2014 2:04 AM, Catalin Marinas wrote: On Tue, Apr 29, 2014 at 05:59:33AM +0100, Jungseok Lee wrote: diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 0fd5650..03ec424 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@

[PATCH v4 6/7] arm64: mm: Implement 4 levels of translation tables

2014-04-28 Thread Jungseok Lee
This patch implements 4 levels of translation tables since 3 levels of page tables with 4KB pages cannot support 40-bit physical address space described in [1] due to the following issue. It is a restriction that kernel logical memory map with 4KB + 3 levels

[PATCH v4 6/7] arm64: mm: Implement 4 levels of translation tables

2014-04-28 Thread Jungseok Lee
This patch implements 4 levels of translation tables since 3 levels of page tables with 4KB pages cannot support 40-bit physical address space described in [1] due to the following issue. It is a restriction that kernel logical memory map with 4KB + 3 levels