Re: [PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-08 Thread Alex Williamson
On Thu, 2013-08-08 at 09:46 -0700, Alexander Duyck wrote: > On 08/07/2013 10:23 PM, Alex Williamson wrote: > > On Wed, 2013-08-07 at 11:30 -0700, Alexander Duyck wrote: > >> On 08/06/2013 07:56 PM, Alex Williamson wrote: > >>> On Tue, 2013-08-06 at 16:27 -0700, Alexander Duyck wrote: > On 08/0

Re: [PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-08 Thread Alexander Duyck
On 08/07/2013 10:23 PM, Alex Williamson wrote: > On Wed, 2013-08-07 at 11:30 -0700, Alexander Duyck wrote: >> On 08/06/2013 07:56 PM, Alex Williamson wrote: >>> On Tue, 2013-08-06 at 16:27 -0700, Alexander Duyck wrote: On 08/05/2013 12:37 PM, Alex Williamson wrote: > The PCI spec indicates

Re: [PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-07 Thread Alex Williamson
On Wed, 2013-08-07 at 11:30 -0700, Alexander Duyck wrote: > On 08/06/2013 07:56 PM, Alex Williamson wrote: > > On Tue, 2013-08-06 at 16:27 -0700, Alexander Duyck wrote: > >> On 08/05/2013 12:37 PM, Alex Williamson wrote: > >>> The PCI spec indicates that with stable power, reset needs to be > >>> a

Re: [PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-07 Thread Alexander Duyck
On 08/06/2013 07:56 PM, Alex Williamson wrote: > On Tue, 2013-08-06 at 16:27 -0700, Alexander Duyck wrote: >> On 08/05/2013 12:37 PM, Alex Williamson wrote: >>> The PCI spec indicates that with stable power, reset needs to be >>> asserted for a minimum of 1ms (Trst). Seems like we should be able >

Re: [PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-06 Thread Alex Williamson
On Tue, 2013-08-06 at 16:27 -0700, Alexander Duyck wrote: > On 08/05/2013 12:37 PM, Alex Williamson wrote: > > The PCI spec indicates that with stable power, reset needs to be > > asserted for a minimum of 1ms (Trst). Seems like we should be able > > to assume power is stable for a runtime seconda

Re: [PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-06 Thread Alexander Duyck
On 08/05/2013 12:37 PM, Alex Williamson wrote: > The PCI spec indicates that with stable power, reset needs to be > asserted for a minimum of 1ms (Trst). Seems like we should be able > to assume power is stable for a runtime secondary bus reset. The > current code has always used 100ms with no ex

[PATCH v4 8/9] pci: Tune secondary bus reset timing

2013-08-05 Thread Alex Williamson
The PCI spec indicates that with stable power, reset needs to be asserted for a minimum of 1ms (Trst). Seems like we should be able to assume power is stable for a runtime secondary bus reset. The current code has always used 100ms with no explanation where that came from. The aer_do_secondary_b