On 6/30/2016 11:37 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Thu, Jun 30, 2016 at 11:32:14AM -0400, Rhyland Klein wrote:
>> On 6/17/2016 11:23 AM, Thierry Reding wrote:
Old Signed by an unknown key
>>>
>>> On Fri, Jun 17, 2016 at 02:49:41PM +0100, Jon Hunter wrote:
>>>
On Thu, Jun 30, 2016 at 11:40:19AM -0400, Rhyland Klein wrote:
> On 6/30/2016 11:37 AM, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> >
> > On Thu, Jun 30, 2016 at 11:32:14AM -0400, Rhyland Klein wrote:
> >> On 6/17/2016 11:23 AM, Thierry Reding wrote:
> Old Signed by an unknown
On Thu, Jun 30, 2016 at 11:32:14AM -0400, Rhyland Klein wrote:
> On 6/17/2016 11:23 AM, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> >
> > On Fri, Jun 17, 2016 at 02:49:41PM +0100, Jon Hunter wrote:
> >> Hi Thierry,
> >>
> >> On 26/05/16 17:41, Rhyland Klein wrote:
> >>> From: Andrew
On 6/17/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Jun 17, 2016 at 02:49:41PM +0100, Jon Hunter wrote:
>> Hi Thierry,
>>
>> On 26/05/16 17:41, Rhyland Klein wrote:
>>> From: Andrew Bresticker
>>>
>>> Move the UTMIPLL initialization code form clk-tegra.c file
Hi Rhyland,
On 27/06/16 19:11, Rhyland Klein wrote:
> Jonathan, can you confirm replacing usleep_range(100, 200) with udelay(2)
> works for you?
Yes for me, using a udelay(2) does seem to work. I have made sure that a
usb device is still detected on the Jetson TX1. However, I am not sure
the bes
; Stephen Warren; Stephen
Boyd; Alexandre Courbot; linux-...@vger.kernel.org;
linux-te...@vger.kernel.org; linux-kernel@vger.kernel.org; Andrew Bresticker
Subject: Re: [PATCH v5] clk: tegra: Initialize UTMIPLL when enabling PLLU
* PGP Signed by an unknown key
On Fri, Jun 17, 2016 at 02:49:41PM +0100
On 6/17/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Jun 17, 2016 at 02:49:41PM +0100, Jon Hunter wrote:
>> Hi Thierry,
>>
>> On 26/05/16 17:41, Rhyland Klein wrote:
>>> From: Andrew Bresticker
>>>
>>> Move the UTMIPLL initialization code form clk-tegra.c file
On Fri, Jun 17, 2016 at 02:49:41PM +0100, Jon Hunter wrote:
> Hi Thierry,
>
> On 26/05/16 17:41, Rhyland Klein wrote:
> > From: Andrew Bresticker
> >
> > Move the UTMIPLL initialization code form clk-tegra.c files into
> > clk-pll.c. UTMIPLL was being configured and set in HW control right
> > a
Hi Thierry,
On 26/05/16 17:41, Rhyland Klein wrote:
> From: Andrew Bresticker
>
> Move the UTMIPLL initialization code form clk-tegra.c files into
> clk-pll.c. UTMIPLL was being configured and set in HW control right
> after registration. However, when the clock init_table is processed and
> chi
On Thu, May 26, 2016 at 12:41:31PM -0400, Rhyland Klein wrote:
> From: Andrew Bresticker
>
> Move the UTMIPLL initialization code form clk-tegra.c files into
> clk-pll.c. UTMIPLL was being configured and set in HW control right
> after registration. However, when the clock init_table is processed
From: Andrew Bresticker
Move the UTMIPLL initialization code form clk-tegra.c files into
clk-pll.c. UTMIPLL was being configured and set in HW control right
after registration. However, when the clock init_table is processed and
child clks of PLLU are enabled, it will call in and enable PLLU as
w
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