Re: [PATCH v5 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

2014-10-27 Thread Mikko Perttunen
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote: Hello Mikko, Hello Vladimir! On 24.10.2014 17:39, Mikko Perttunen wrote: From: Tuomas Tynkkynen Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is

Re: [PATCH v5 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

2014-10-27 Thread Mikko Perttunen
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote: Hello Mikko, Hello Vladimir! On 24.10.2014 17:39, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124

Re: [PATCH v5 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

2014-10-24 Thread Vladimir Zapolskiy
Hello Mikko, On 24.10.2014 17:39, Mikko Perttunen wrote: > From: Tuomas Tynkkynen > > Add shared code to support the Tegra DFLL clocksource in open-loop > mode. This root clocksource is present on the Tegra124 SoCs. The > DFLL is the intended primary clock source for the fast CPU cluster. > >

[PATCH v5 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

2014-10-24 Thread Mikko Perttunen
From: Tuomas Tynkkynen Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul Walmsley from

[PATCH v5 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

2014-10-24 Thread Mikko Perttunen
From: Tuomas Tynkkynen ttynkky...@nvidia.com Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul

Re: [PATCH v5 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

2014-10-24 Thread Vladimir Zapolskiy
Hello Mikko, On 24.10.2014 17:39, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast