On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote:
Hello Mikko,
Hello Vladimir!
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote:
Hello Mikko,
Hello Vladimir!
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124
Hello Mikko,
On 24.10.2014 17:39, Mikko Perttunen wrote:
> From: Tuomas Tynkkynen
>
> Add shared code to support the Tegra DFLL clocksource in open-loop
> mode. This root clocksource is present on the Tegra124 SoCs. The
> DFLL is the intended primary clock source for the fast CPU cluster.
>
>
From: Tuomas Tynkkynen
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.
This code is very closely based on a patch by Paul Walmsley from
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.
This code is very closely based on a patch by Paul
Hello Mikko,
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast
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