Hi Rob,
On 6/1/2020 6:46 AM, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 5/28/2020 3:36 AM, Kishon Vijay Abraham I wrote:
>> Hi Rob,
>>
>> On 5/27/2020 10:07 PM, Rob Herring wrote:
>>> On Wed, May 27, 2020 at 4:49 AM Kishon Vijay Abraham I
>>> wrote:
Hi Rob,
On 5/26/2020
Hi Rob,
On 5/28/2020 3:36 AM, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 5/27/2020 10:07 PM, Rob Herring wrote:
>> On Wed, May 27, 2020 at 4:49 AM Kishon Vijay Abraham I wrote:
>>>
>>> Hi Rob,
>>>
>>> On 5/26/2020 8:42 PM, Rob Herring wrote:
On Sun, May 24, 2020 at 9:30 PM Kishon Vijay
Hi Rob,
On 5/27/2020 10:07 PM, Rob Herring wrote:
> On Wed, May 27, 2020 at 4:49 AM Kishon Vijay Abraham I wrote:
>>
>> Hi Rob,
>>
>> On 5/26/2020 8:42 PM, Rob Herring wrote:
>>> On Sun, May 24, 2020 at 9:30 PM Kishon Vijay Abraham I
>>> wrote:
Hi Rob,
On 5/22/2020 9:24 PM,
On Wed, May 27, 2020 at 4:49 AM Kishon Vijay Abraham I wrote:
>
> Hi Rob,
>
> On 5/26/2020 8:42 PM, Rob Herring wrote:
> > On Sun, May 24, 2020 at 9:30 PM Kishon Vijay Abraham I
> > wrote:
> >>
> >> Hi Rob,
> >>
> >> On 5/22/2020 9:24 PM, Rob Herring wrote:
> >>> On Thu, May 21, 2020 at 9:37 PM
Hi Rob,
On 5/26/2020 8:42 PM, Rob Herring wrote:
> On Sun, May 24, 2020 at 9:30 PM Kishon Vijay Abraham I wrote:
>>
>> Hi Rob,
>>
>> On 5/22/2020 9:24 PM, Rob Herring wrote:
>>> On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I
>>> wrote:
Certain platforms like TI's J721E using
On Sun, May 24, 2020 at 9:30 PM Kishon Vijay Abraham I wrote:
>
> Hi Rob,
>
> On 5/22/2020 9:24 PM, Rob Herring wrote:
> > On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I
> > wrote:
> >>
> >> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> >> 32-bit accesses
Hi Rob,
On 5/22/2020 9:24 PM, Rob Herring wrote:
> On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I wrote:
>>
>> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
>> 32-bit accesses for reading or writing to Cadence registers. Convert all
>> read and write accesses
On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I wrote:
>
> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> 32-bit accesses for reading or writing to Cadence registers. Convert all
> read and write accesses to 32-bit in Cadence PCIe driver in preparation
> for
Certain platforms like TI's J721E using Cadence PCIe IP can perform only
32-bit accesses for reading or writing to Cadence registers. Convert all
read and write accesses to 32-bit in Cadence PCIe driver in preparation
for adding PCIe support in TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham
9 matches
Mail list logo