Re: [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting

2020-06-30 Thread chao hao
On Mon, 2020-06-29 at 12:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > MT8173 is different from other SoCs for MMU_CTRL register. > > For mt8173, its bit9 is in_order_write_en and doesn't use its > > default 1'b1.> For other SoCs, bit[12] represents victim_tlb_en f

Re: [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting

2020-06-29 Thread Matthias Brugger
On 29/06/2020 09:13, Chao Hao wrote: > MT8173 is different from other SoCs for MMU_CTRL register. > For mt8173, its bit9 is in_order_write_en and doesn't use its > default 1'b1.> For other SoCs, bit[12] represents victim_tlb_en feature and > victim_tlb is enable defaultly(bit[12]=1), if we use >