Re: [PATCH v5 1/1] fpga: dfl: afu: harden port enable logic

On 2/6/21 12:46 PM, Moritz Fischer wrote: > Russ, > > On Fri, Feb 05, 2021 at 10:25:21AM -0800, Russ Weight wrote: >> Port enable is not complete until ACK = 0. Change >> __afu_port_enable() to guarantee that the enable process >> is complete by polling for ACK == 0. >> >> Reviewed-by: Tom Rix

Re: [PATCH v5 1/1] fpga: dfl: afu: harden port enable logic

Russ, On Fri, Feb 05, 2021 at 10:25:21AM -0800, Russ Weight wrote: > Port enable is not complete until ACK = 0. Change > __afu_port_enable() to guarantee that the enable process > is complete by polling for ACK == 0. > > Reviewed-by: Tom Rix > Reviewed-by: Matthew Gerlach > Signed-off-by: Russ

[PATCH v5 1/1] fpga: dfl: afu: harden port enable logic

Port enable is not complete until ACK = 0. Change __afu_port_enable() to guarantee that the enable process is complete by polling for ACK == 0. Reviewed-by: Tom Rix Reviewed-by: Matthew Gerlach Signed-off-by: Russ Weight --- v5: - Added Reviewed-by tag to commit message v4: - Added a dev_wa