Re: [PATCH v5 1/1] pinctrl: armada-37xx: Add irqchip support

On Fri, Apr 28, 2017 at 4:01 PM, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can > only manage the edge ones. > > The way the interrupt are managed is classical so we can use the generic > interrupt chip model. >

Re: [PATCH v5 1/1] pinctrl: armada-37xx: Add irqchip support

On Fri, Apr 28, 2017 at 4:01 PM, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can > only manage the edge ones. > > The way the interrupt are managed is classical so we can use the generic > interrupt chip model. > > The only unusual "feature" is

[PATCH v5 1/1] pinctrl: armada-37xx: Add irqchip support

The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed is classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller.

[PATCH v5 1/1] pinctrl: armada-37xx: Add irqchip support

The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed is classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller.