Re: [PATCH v5 16/20] memory: mtk-smi: Add bus_sel for mt8183

2019-01-30 Thread Yong Wu
On Wed, 2019-01-30 at 11:07 -0800, Evan Green wrote: > On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote: > > > > There are 2 mmu cells in a M4U HW. we could adjust some larbs entering > > mmu0 or mmu1 to balance the bandwidth via the smi-common register > > SMI_BUS_SEL(0x220)(Each larb occupy 2 bits)

Re: [PATCH v5 16/20] memory: mtk-smi: Add bus_sel for mt8183

2019-01-30 Thread Evan Green
On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote: > > There are 2 mmu cells in a M4U HW. we could adjust some larbs entering > mmu0 or mmu1 to balance the bandwidth via the smi-common register > SMI_BUS_SEL(0x220)(Each larb occupy 2 bits). > > In mt8183, For better performance, we switch larb1/2/5/7

[PATCH v5 16/20] memory: mtk-smi: Add bus_sel for mt8183

2018-12-31 Thread Yong Wu
There are 2 mmu cells in a M4U HW. we could adjust some larbs entering mmu0 or mmu1 to balance the bandwidth via the smi-common register SMI_BUS_SEL(0x220)(Each larb occupy 2 bits). In mt8183, For better performance, we switch larb1/2/5/7 to enter mmu1 while the others still keep enter mmu0. In m