On 7/3/2019 12:37 AM, Paolo Bonzini wrote:
On 20/06/19 11:46, Xiaoyao Li wrote:
You cannot put the atomic switch here. What if umwait_control_cached is changed
at runtime? Host kernel patch exposed a sysfs interface to let it happen.
Thanks for the review, Xiaoyao. I agree with both of your
On 20/06/19 11:46, Xiaoyao Li wrote:
> You cannot put the atomic switch here. What if umwait_control_cached is
> changed
> at runtime? Host kernel patch exposed a sysfs interface to let it happen.
Thanks for the review, Xiaoyao. I agree with both of your remarks.
Paolo
>> +break;
On Thu, 2019-06-20 at 16:46 +0800, Tao Xu wrote:
> UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
> to determines the maximum time in TSC-quanta that the processor can reside
> in either C0.1 or C0.2.
>
> This patch emulates MSR IA32_UMWAIT_CONTROL in guest and
On Thu, 2019-06-20 at 16:46 +0800, Tao Xu wrote:
> UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
> to determines the maximum time in TSC-quanta that the processor can reside
> in either C0.1 or C0.2.
>
> This patch emulates MSR IA32_UMWAIT_CONTROL in guest and
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can reside
in either C0.1 or C0.2.
This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
IA32_UMWAIT_CONTROL between host and guest. The
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