On Mon, Jun 24, 2019 at 12:39:05AM +0200, Thomas Gleixner wrote:
> On Wed, 19 Jun 2019, Fenghua Yu wrote:
> >
> > +#define MSR_IA32_UMWAIT_CONTROL0xe1
> > +#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLED BIT(0)
> > +#define MSR_IA32_UMWAIT_CONTROL_MAX_TIME 0xfffc
>
>
On Wed, 19 Jun 2019, Fenghua Yu wrote:
>
> +#define MSR_IA32_UMWAIT_CONTROL 0xe1
> +#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLED BIT(0)
> +#define MSR_IA32_UMWAIT_CONTROL_MAX_TIME 0xfffc
Errm, no! That's not maxtime, that's the time field mask in the
MSR. Throughout
umwait or tpause allows processor to enter a light-weight
power/performance optimized state (C0.1 state) or an improved
power/performance optimized state (C0.2 state) for a period
specified by the instruction or until the system time limit or until
a store to the monitored address range in umwait.
3 matches
Mail list logo
